72 bit memory is commonly known as ECC memory. It has an additional 8 bits for Error Correction Check 64 bit memory is non-ECC. 72 bit or 64 bit configuration are typically found in 168 pin DIMMs
36 bit memory is commonly known as parity memory. It has an additional 4 bits for parity checking. 32 bit memory is non-parity. 32 bit or 36 bit configuration are typically found in 72pin or 30 pin SIMMs
Well the truth is :
The SDRAM has multiple internal banks. The 16M SDRAM has 2 banks, the 64M has 4 banks. When you tell the SDRAM a ROW or COLUMN address you must also specify which BANK you are referring to. The way to do this is by the 'bank address' (BA). Herein lies the problem.
For some unknown reasons, suppliers have lumped together the ROW address pins with the BANK address pins and simply refer to them as 'address' pins. For the 2Mx8 SDRAM some suppliers claim to have 11 ROW address plus 1 BA, other just say 12 addresses. That's just addressing, for refresh requires you also specify the refresh interval (tREF). For a distributed refresh scheme you simply divide tREF by the number of refresh cycles to get the auto-refresh interval. In both cases for the SDRAM it works out like:
The upshot is that for distributed refresh schemes these two devices are identical in both addressing and refresh. (For a burst refresh scheme, the 32ms tREF is a subset of the 64ms.)
For the general PC application the 2K device works fine. The 4K device offers no advantage. Note that this is not the case for asynchronous DRAM where there truly is a difference in addressing between 2K and 4K.
High density DIMMs have lots of chips on them and therefore possess a higher capacitive load on the address and control signals in comparison to lower density DIMMs. Some designers use re-drive buffers on the DIMM to boost the signals to reduce system loading when compared to the same high density module without buffers. But,
the buffers introduce a small delay into the electrical signal, so adding buffers to a standard density module would have the effect of slowing down the signal, compared to the same low density module without buffers.
CL stands for CAS Latency. It is a programmable register in the SDRAM that sets the number of clock cycles between the issuance of the READ command and when the data comes out. Smaller number for CL indicates faster SDRAM within the same frequency.
SDRAM, EDO and FPM chips look similar to each other. The best way to tell the difference is to reference the part number on the chip. Most DRAM manufacturers have reference books or lists on their web sites. By looking at a memory module one can attempt to guess what it is. A general guideline is to look at the IC type and size. The EDO and FPM chips are typically packaged in SOJ form and are thicker when compared to that of the SDRAM chips which are typically packaged in slim-line TSOP form. The EDO/FPM chips typically have a marking of -60 at the end of the string of numbers and that of the SDRAM chips typically have markings of -12 -10 -8 -7.5. A SDRAM module typically has a row of the resistor or resistor arrays above the contact tabs.
A memory module is made up of electrical cells. The refresh process recharges these cells, which are arranged on the chips in rows. The refresh cycle refers to the number of rows that must be refreshed.
The common refresh cycles are 2K, 4K and 8K. Refresh cycle together with refresh period determines how often refresh is needed, which is defined as Refresh Rate.
For the same refresh period, 4K refresh parts needs to be refreshed more frequently than 2K parts. For the same size DRAM, 4K refresh part consume less power than 2K refresh parts.
Some specially design DRAMs feature self refresh technology, which enables the components to refresh on their own -- independent from the CPU or external refresh circuits.
Self refresh, which is built into the DRAM itself, reduces power consumption, and it is commonly used in notebook computers
EDO DRAM speeds up memory transactions by as little as 5% or by as much as 25% over conventional DRAM, depending upon how much Cache you have on your motherboard. Less Cache on the motherboard will result in a larger speed increase when adding EDO DRAM. EDO eliminates a wait state between the execution of sequential-read commands from memory, giving the CPU significantly faster access to memory.
It means you may experience system errors in a 100mhz system because the memory's performance cannot keep up with the system requirement. The system will operate at the speed of the slowest component. For example, installing 66MHz SDRAM memory in a PC-100 system will cause the bus to operate at 66MHz, rather than the speed it was designed to operate at.
A PC100 or PC133 compliant memory includes a label affixed to it which identifies the module as "PC100 compliant" or "PC133 compliant" . An attempt can be made to verify it by looking at the chip marking which should indicate "-8" or "-7.5" after the string of manufacturer part number, though this may not be entirely accurate.
The early SDRAM DIMM design has 2 clock inputs to drive all the SDRAM chip. This was found to be insufficient due to loading on these inputs. Some 4 clock modules will not work in systems that are designed for 2 clock, but some will. SOME 2 clock modules might not work in systems designed for 4 clocks, but then again some will.
4 clock modules are the current standard and it is unlikely to change again.
PC SDRAM is a loose general term for SDRAM that runs at 66 MHz and has an SPD chip for compatibility with P-II motherboards.
PC100 SDRAM refers to PC100 SDRAM chips or DIMMs that meet INTEL PC100 qualification standard. These parts are designed to run at 100 Mhz front side bus (FSB) speeds.
Registered SDRAM - This is SDRAM module with Register for Address and Control Signals. Registered DIMMs reduce the loading of DIMM to the motherboard so that larger capacity DIMM modules and more DIMMs can be populated on a motherboard.
It is a technique used widely on servers to increae the amount of memory the system can support. The Registered DIMM is a little slower in access timing versus that of the unbuffered counterpart.